{"id":6470,"date":"2024-05-28T11:11:42","date_gmt":"2024-05-28T03:11:42","guid":{"rendered":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/?p=6470"},"modified":"2024-05-28T11:12:07","modified_gmt":"2024-05-28T03:12:07","slug":"202405270002","status":"publish","type":"post","link":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/2024\/05\/28\/202405270002\/","title":{"rendered":"Announcement on the Release of the 2024 Project Guidelines for the Major Research Program on Basic Research of New Devices in the Post-Moore Era"},"content":{"rendered":"\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t\n\t\t\t\t\t\t<\/span>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t\t
\n\t\t\t\t

Announcement on the Release of the 2024 Project Guidelines\u00a0for the Major Research Program on Basic Research of New Devices in the Post-Moore Era<\/strong><\/p>

Major research project on basic research of new devices in the post-Moore era <\/strong>2024 Project Guide<\/strong><\/p>

This major research program is aimed at the country’s major strategic needs for independent chip development. It focuses on basic chip issues and aims to develop new devices and computing architectures in the post-Moore era, break through the bottleneck of chip computing power, promote the improvement of my country’s chip research level, and support my country’s scientific and technological innovation in the chip field.<\/p>

\u3000\u3000\u00a01. Scientific Objectives<\/strong>\u00a0<\/p>

This major research plan is aimed at the future chip computing power issues and focuses on the forefront of chip development. It plans to make breakthroughs in new mechanisms of ultra-low energy information processing, new mechanisms of carrier approximate ballistic transport, new materials with high mobility and high state density, new methods of high-density integration, and new non-von Schroeder computing architectures through the cross-integration of multiple disciplines such as information, mathematics, physics, materials, engineering, and life. It aims to develop ultra-low power devices with switching energy consumption below 1fJ and high-performance devices that exceed the carrier transport speed limit of silicon-based CMOS, achieve non-von Schroeder architecture chips with a computing power increase of more than 2 orders of magnitude, develop transformative basic devices, integration methods, and computing architectures, cultivate a research team with international influence, and enhance my country’s independent innovation capabilities and international status in the chip field.<\/p>

\u3000\u3000\u00a02. Core Scientific Issues<\/strong><\/p>

\u3000\u3000In order to solve the computing bottleneck of chip technology in the post-Moore era, we conducted research around the following three core scientific issues:<\/p>

\u3000\u30001. Energy consumption boundary and breakthrough mechanism of CMOS devices.<\/p>

\u3000\u3000The following key issues need to be addressed: exploring the energy consumption boundary of CMOS devices for single information processing, studying new mechanisms to break through this boundary, and realizing data calculation, storage and transmission with ultra-low energy consumption.<\/p>

\u3000\u3000(ii) Device mechanism that breaks through silicon-based speed limits.<\/p>

\u3000\u3000The following key issues need to be addressed: Based on the exploration of new material systems that have both long carrier free paths and high state density, the device mechanism of approximate ballistic transport should be studied to achieve high-performance devices that break through the silicon-based carrier velocity limit.<\/p>

\u3000\u3000(3) Mechanisms that surpass the energy efficiency of the classic von Neumann architecture.<\/p>

The following key issues need to be addressed: exploring the mechanisms and methods for the integration of computing and storage, and combining new information coding paradigms to realize new computing architectures and break through the energy efficiency bottleneck of the von Neumann architecture.<\/p>

\u3000\u30003. Key research directions for 2024<\/strong><\/p>

\u3000\u30001. Cultivation projects<\/p>

\u3000\u3000Focusing on the above scientific issues and guided by the overall scientific goals, we plan to fund five cultivation projects with strong exploratory nature, novel topics, and good preliminary research foundation. The research directions include but are not limited to the following:<\/p>

\u3000\u30001. Theory, materials and integration technology of ultra-low power devices.<\/p>

\u3000\u3000Aiming at the switching energy consumption target of less than 1fJ, we study new principle logic, memory devices and their core materials and integration technologies that go beyond CMOS; we study extremely low power information processing and storage mechanisms and models under extreme physical conditions.<\/p>

\u3000\u30002. Theory, materials and integration technology of high-speed and high-performance devices.<\/p>

\u3000\u3000Explore ballistic transport mechanisms, seek new silicon-based compatible semiconductor materials with high mobility and high state density, research and realize new field-effect devices with high ballistic transport coefficients; explore new mechanisms and device technologies for high-speed information processing, access and transmission under limited energy consumption.<\/p>

\u3000\u30003. Highly energy-efficient computing and storage architecture.<\/p>

\u3000\u3000Explore new computing and storage architectures that break through the von Neumann energy efficiency bottleneck, and study design methodologies for new in-memory computing architectures.<\/p>

\u3000\u3000(2) Key support projects.<\/p>

\u3000\u3000Focusing on core scientific issues and guided by the overall scientific goals, it is planned to fund six key support projects that have accumulated good previous research results, are at the forefront of current hot topics, and have made great contributions to the overall goals. The directions are as follows:<\/p>

\u3000\u30001.Ballistic transport devices at ultra-low temperatures.<\/p>

\u3000\u3000Aiming at the demand for low power consumption and high performance, we developed a low-temperature ballistic transport device. When the gate overdrive voltage and the drain voltage are both less than 0.5 V at an operating temperature below 77K, the device current switching ratio reaches more than 9 orders of magnitude, the device ballistic transport coefficient is greater than 0.8, and the carrier injection velocity is greater than 1\u00d710\u00a07<\/sup>\u00a0cm\/s. We established a low-temperature device PDK below 77K, and designed an 8-bit microprocessor that works at low temperatures below 77K. Experiments have verified that its speed and power consumption performance are more than 1 times better than the room temperature performance, providing an engineerable solution for surpassing existing silicon-based high-performance computing technology.<\/p>

\u3000\u30002. High mobility stacked channel gate-all-around CMOS device.<\/p>

\u3000\u3000Aiming at the needs of high-performance applications, a multi-layer gate-all-around CMOS device with high-mobility stacked channel has been developed. The number of channel layers is not less than 3. The on-state current of NMOS and PMOS is greater than 600 \u03bcA\/\u03bcm when the operating voltage is 0.7 V. The absolute value deviation of the threshold voltage of NMOS and PMOS is less than 100 mV, and the switching ratio is greater than 10\u00a06<\/sup>\u00a0.<\/p>

\u3000\u30003. Research on highly robust SRAM storage and computing integrated architecture and its large-scale expansion architecture.<\/p>

\u3000\u3000Research the digital domain SRAM (random static memory) storage and computing integrated architecture and its high robustness design scheme, research the high computing power density SRAM storage and computing integrated architecture technology for fixed-point, floating-point and variable precision, with a single chip computing power of not less than 4 TOPS, supporting mainstream computing precision such as INT8\/BF16, and supporting tensor operators in large models; research the computing power scalable architecture and efficient compilation method for large model applications, with a computing power of not less than 100 TOPS@INT8, 50 TFLOPS@BF16, to solve the computing power expansion problem of the SRAM storage and computing integrated architecture.<\/p>

\u3000\u30004. Research on heterogeneous storage and computing architecture integrating different storage media.<\/p>

\u3000\u3000The research focuses on heterogeneous integration methods that integrate new non-volatile high-density memories with volatile high-speed and high-durability memories, the fusion design of near-memory and in-memory computing circuits, multi-operator flexible programmable architecture technology, and heterogeneous storage and computing integrated architecture chips that integrate different storage media. It supports multiple data precisions such as INT8 and BF16, with a computing energy efficiency of >20 TOPS\/W@INT8, and supports multiple tensor operators of mainstream artificial intelligence algorithms such as large models and machine vision, achieving a significant improvement in computing power density and energy efficiency.<\/p>

\u3000\u30005. Research on high-precision simulation computing architecture for scientific computing.<\/p>

\u3000\u3000Research high-precision solution methods and circuit topologies for linear matrix equations, nonlinear matrix equations, and differential equations based on analog computing mechanisms, and research analog computing architectures for scientific computing or AI for Science; the matrix solution scale is no less than 1024\u00d71024, and the accuracy is no less than 32-bit floating point numbers; under FP32 solution accuracy, power consumption is reduced by 2 orders of magnitude and solution delay is reduced by 1 order of magnitude.<\/p>

\u3000\u30006. Design methods for heterogeneous many-core architectures for new computing devices.<\/p>

\u3000\u3000Research on general and scalable heterogeneous many-core architecture design methods for new computing devices. Build application analysis models to obtain design requirements such as “special-general” heterogeneous computing power and storage bandwidth; build architecture design languages \u200b\u200bto describe heterogeneous computing cores, many-core data flows, storage hierarchies, and interconnections based on new computing devices; research on automated generation and optimization methods for heterogeneous many-core architectures to improve the design indicators of the architecture. Develop tool prototypes based on the above methods, select typical devices and applications to design heterogeneous many-core architectures, with dedicated computing power not less than 64 TOPS@INT8 and general computing power not less than 6 TOPS@INT8.<\/p>

\u3000\u3000(3) Integration projects<\/p>

\u3000\u3000It is planned to select three integrated projects with significant application value and good research foundation for funding. The directions are as follows:<\/p>

\u3000\u30001. Two-dimensional semiconductor technology for large-scale CMOS integration.<\/p>

\u3000\u3000In response to the demand for ultra-low power devices in the post-Moore era, we study single-atom-layer two-dimensional semiconductor materials, devices, EDA and processes for large-scale CMOS integration to solve the bottlenecks of miniaturization and power consumption faced by silicon-based CMOS technology. We develop methods for preparing N-type and P-type two-dimensional semiconductor single crystals to achieve the preparation of continuous thin films of two-dimensional semiconductor single crystals on 8-inch silicon-based substrates; we study the integration process of two-dimensional semiconductor devices to achieve CMOS logic gate units based on two-dimensional semiconductors, where the device gate dielectric equivalent oxide layer thickness (EOT) is \u22641 nm, the ohmic contact resistance is \u2264100 \u03a9\u00b7\u03bcm (contact length \u226420 nm), and the on-state current density is \u22651 mA\/\u03bcm at 1 V source-drain voltage; we develop device-process-circuit collaborative optimization strategies to develop thousand-gate-level two-dimensional semiconductor logic chips to achieve key logic function verification.<\/p>

\u3000\u30002. RISC-V and storage and computing heterogeneous fusion chip.<\/p>

\u3000\u3000Aiming at the needs of high computing density, computing completeness, and autonomous and controllable ecology for artificial intelligence applications such as large models, we study the design of heterogeneous fusion architecture of SRAM storage and computing and high-performance RISC-V processors, multi-core scalable architecture and high-speed interconnection design, and full-stack heterogeneous computing compilation and software stack. We have completed the storage and computing extension instruction set based on high-performance RISC-V processor cores, including no less than 10 extension instructions, and realized a prototype of heterogeneous computing chip. The computing density of AI computing modules is greater than 5.92 TPP\/mm2. We\u00a0have<\/sup>\u00a0completed the design of multi-core heterogeneous scalable computing architecture and its simulator, with the computing power of the architecture being no less than 100 TOPS@INT8. We have completed the RISC-V heterogeneous compilation full-stack software tool chain, and realized efficient compilation and automated program deployment for heterogeneous multi-core chips.<\/p>

\u3000\u30003. Data-driven storage and computing integrated computing architecture.<\/p>

Aiming at the high computing power and high energy efficiency requirements of artificial intelligence, we study the storage-computing integrated computing architecture that combines data-driven digital computing with in-memory computing and develop verification chips. We study the data encoding method and computing principle of the storage-computing integrated architecture, explore data-driven storage-computing collaborative data flow, design circuits, system architectures and parallel methods that are suitable for storage-computing integration, and solve the difficult problem of high energy efficiency, high precision and high flexibility in intelligent computing chips. We develop data-driven storage-computing integrated computing chips that support variable computing precision, support >10 linear and nonlinear operators, peak computing energy efficiency >40 TOPS\u00b7bit\/W, storage-computing array performance density >12 TOPS\u00b7bit\/mm\u00a02<\/sup>\u00a0, storage capacity >1 Mb, storage density >1 Mb\/mm\u00a02<\/sup>\u00a0, and complete verification on typical artificial intelligence models.<\/p>

\u3000\u30004. Basic Principles of Project Selection<\/strong><\/p>

\u3000\u30001. Focusing on core scientific issues, we will encourage valuable frontier exploration and innovative research.<\/p>

\u3000\u3000(II) Priority will be given to research projects that can solve practical problems in chips and have application prospects.<\/p>

\u3000\u3000(3) Encourage interdisciplinary research involving mathematics, physics, engineering, materials, life sciences, etc.<\/p>

(4) Priority will be given to supporting research projects that have a sound research foundation and previous accumulation and that make a direct contribution to the overall goals.<\/p>

\u3000\u30005. Funding Plan for 2024<\/strong><\/p>

In 2024, it is planned to fund 5 cultivation projects, with an average direct cost funding intensity of about 800,000 yuan per project, and a funding period of 3 years. The research period in the application form for the cultivation project should be filled in as “January 1, 2025-December 31, 2027”; it is planned to fund 6 key support projects, with an average direct cost funding intensity of about 3 million yuan per project, and a funding period of 3 years. The research period in the application form for the key support project should be filled in as “January 1, 2025-December 31, 2027”. It is planned to fund 3 integrated projects, with an average direct cost funding intensity of about 15 million yuan per project, and a funding period of 3 years. The research period in the application form for the integrated project should be filled in as “January 1, 2025-December 31, 2027”.<\/p>

\u3000\u30006. Application Requirements and Notes<\/strong><\/p>

\u3000\u30001. Application conditions<\/p>

\u3000\u3000Applicants for this major research project should meet the following conditions:<\/p>

\u3000\u30001. Have experience in undertaking basic research projects;<\/p>

\u3000\u30002. Possess a senior professional and technical position (title).<\/p>

\u3000\u3000Postdoctoral researchers, those pursuing a graduate degree, and those who do not have a job or whose unit is not a supporting unit are not allowed to apply as applicants.<\/p>

\u3000\u30002. Regulations on application limits.<\/p>

Implement the relevant requirements for limited application in the “Application Regulations” of the “2024 National Natural Science Foundation Project Guide”.<\/p>

\u3000\u30003. Notes on application<\/p>

Applicants and supporting institutions should carefully read and implement the relevant requirements of this project guide, the “2024 National Natural Science Foundation Project Guide” and the “Notice on the Application and Completion of the 2024 National Natural Science Foundation Project and Other Related Matters”.<\/p>

\u3000\u30001. This major research project adopts paperless application. The application submission period is from 16:00 on June 24 to July 1, 2024.<\/strong><\/p>

\u3000\u3000(1) Applicants should fill in and submit the electronic application form and attached materials online in accordance with the filling instructions and writing outline requirements for major research project projects in the Science Foundation Network Information System (hereinafter referred to as the Information System).<\/p>

\u3000\u3000(2) This major research program aims to closely focus on core scientific issues, provide strategic direction guidance and integrate advantages of multidisciplinary related research to form a project cluster. Applicants should independently formulate project names, scientific objectives, research contents, technical routes and corresponding research funds based on the specific scientific issues to be solved by this major research program and the research directions to be funded as announced in the project guidelines.<\/p>

\u3000\u3000(3) Select \u201cMajor Research Program\u201d as the funding category in the application form, select \u201cCultivation Project\u201d, \u201cKey Support Project\u201d or \u201cIntegration Project\u201d as the subcategory, select \u201cBasic Research on New Devices in the Post-Moore Era\u201d as the annotation, and select the corresponding application code based on the specific research content of the application.<\/p>

\u3000\u3000The number of cooperative research units for cultivation projects and key support projects shall not exceed 2. The number of cooperative research units for integrated projects shall not exceed 4.<\/p>

\u3000\u3000(4) In the \u201cBasis for Project Establishment and Research Content\u201d section of the application, the applicant should first clearly state that the application is in line with the key research directions in the project guidelines, as well as the contribution of the application to solving the core scientific problems of this major research plan and achieving the scientific goals of this major research plan.<\/p>

\u3000\u3000If the applicant has undertaken other scientific and technological projects related to this major research program, he\/she should discuss the differences and connections between the application project and other related projects in the “Research Foundation and Working Conditions” section of the application body.<\/p>

\u3000\u30003. Other matters needing attention.<\/p>

\u3000\u3000(1) In order to achieve the overall scientific goals and multidisciplinary integration of the major research program, the project leaders who receive funding should commit to comply with the relevant regulations on data and information management and sharing, and during the implementation of the project, they should pay attention to the mutual support relationship between the project and other projects in this major research program.<\/p>

(2) In order to strengthen academic exchanges among projects, promote the formation of project clusters and multidisciplinary cross-cutting and integration, this major research program will hold an annual academic exchange meeting for funded projects and will organize academic seminars in related fields from time to time. The project leaders of the funded projects are obliged to participate in the above-mentioned academic exchange activities organized by the Guiding Expert Group and the Management Working Group of this major research program.<\/p>

\u3000\u30004. Consultation methods<\/p>

\u3000\u3000Information Science Department, National Natural Science Foundation of China<\/p>

\u3000\u3000Contact number: 010-62327351<\/p>\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

\n\t\t\t\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\tDownload in Word document<\/span>\n\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

Program ID<\/b>: 202405270002
\nSubmission Deadline<\/b>: July 1, 2024
\nAward Size<\/b>: <\/p>\n","protected":false},"author":182,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[25],"tags":[],"funding-level":[40],"subject":[],"keyword":[],"_links":{"self":[{"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/posts\/6470"}],"collection":[{"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/users\/182"}],"replies":[{"embeddable":true,"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/comments?post=6470"}],"version-history":[{"count":3,"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/posts\/6470\/revisions"}],"predecessor-version":[{"id":6477,"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/posts\/6470\/revisions\/6477"}],"wp:attachment":[{"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/media?parent=6470"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/categories?post=6470"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/tags?post=6470"},{"taxonomy":"funding-level","embeddable":true,"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/funding-level?post=6470"},{"taxonomy":"subject","embeddable":true,"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/subject?post=6470"},{"taxonomy":"keyword","embeddable":true,"href":"https:\/\/sites.gtiit.edu.cn\/ResearchIntranet\/wp-json\/wp\/v2\/keyword?post=6470"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}