Notice on Issuing the 2023 Annual Project Guide of the Major Research Plan of the Frontier Technology and Scientific Foundation of Integrated Chips
Major research program on the scientific basis of integrated chip frontier technology 2023 project guide
The major research plan of “Scientific Basis of Advanced Technology of Integrated Chip” faces the major strategic needs of the country’s high-performance integrated circuits and focuses on the major basic problems of integrated chips. By tackling key problems in the fields of mathematical basis of integrated chips, key technologies of information science and physical theory of process integration, it promotes the improvement of chip research level in China and provides basic theoretical and technical support for the development of new paths for improving chip performance.
1. Scientific objectives
This major research plan is oriented to the cutting-edge technology of integrated chips, focusing on the brand-new problems brought about by the great improvement of the integration degree (quantity and type) of cores. It is planned to explore the new principles of decomposition, combination and integration of integrated chips through the deep intersection and integration of integrated circuit science and engineering, computer science, mathematics, physics, chemistry and materials, and develop a new technical path to improve the performance of chips by 1-2 orders of magnitude based on independent integrated circuit technology, and cultivate an internationally influential research team.
2. Core scientific issues
This major research plan aims at the decomposition, combination and integration problems of integrated chips after the number and variety of cores have been greatly improved, and focuses on the following three core scientific issues:
(1) Mathematical description and combinatorial optimization theory of core particles.
Explore the abstract mathematical description method of integrated chip and core, and construct the mapping, simulation and optimization theory of integrated chip to core with complex functions.
(2) Large-scale parallel architecture and design automation.
Explore the design methodology of integrated chips after the core-particle integration has been greatly improved, and study the multi-core interconnection architecture, circuits, layout and wiring methods to support the design of 100-core/10,000-core scale integrated chips.
(3) Core-particle scale multi-physical field coupling mechanism and interface theory.
Clarify the coupling mechanism of electric-thermal-mechanical multi-physical fields in the integrated chip under the three-dimensional structure, and construct a fast and accurate simulation calculation method of multi-physical fields and multi-interface coupling at the core-particle scale to support the design and manufacture of 3D integrated chips.
3. Research direction of funding in 2023
(1) Cultivation projects.
Based on the above-mentioned scientific problems and guided by the overall scientific goal, in 2023, it is planned to give priority to the application projects with strong exploration, original ideas and new technology paths around the following research directions:
- Decomposition and combination of core particles and reusable design method.
The formal description of integrated chips and chips, decomposition-combination theory and modeling method are studied, and the reusable design methods of computing/storage/interconnection/power/sensing/RF chips are studied.
- Multi-core parallel processing and interconnection architecture.
This paper studies the high computing power and extensible architecture for 2.5D/3D integration, the interconnection network and fault-tolerant mechanism between computing/storage/communication cores, and the multi-core heterogeneous compilation tool chain.
- Integrated chip multi-field simulation and EDA.
The calculation method and rapid simulation tools of electro-thermal-mechanical coupling multi-physical fields for core-particle scale, integrated/layout/routing automation design tools for integrated chips, testability design of integrated chips and so on are studied.
- Integrated chip circuit design technology.
Research the high-speed, energy-efficient serial/parallel, RF, silicon optical interface circuits for 2.5D/3D integration, power management circuits and systems for high-power integrated chips, etc.
- Integrated chip 2.5D/3D technology.
The manufacturing technology of large-size silicon Interposer, high-density, high-reliability 2.5D/3D integration technology and materials, the heat dissipation method of 10,000-watt chip, and the optoelectronic integrated packaging technology are studied.
(2) Key support projects.
Based on the core scientific issues of this major research plan and guided by the overall scientific goal, in 2023, it is planned to give priority to the application projects with good accumulation of previous research results, strong cross-cutting nature and great contribution to the overall scientific goal:
- High-performance integrated chip fault-tolerant interconnection architecture.
The fault-tolerant interconnection architecture of large-scale 2.5D/3D integrated chips is studied, and the reconfigurable interconnection topology and fault-tolerant routing mechanism under multi-core integration are explored. Interconnection architecture supports dynamic reconfiguration of various interconnection topologies at the scale of 100-core/10,000-core, and fault-tolerant mechanism can tolerate nuclear faults, inter-core faults and inter-core interconnection faults. Realize the interconnection architecture simulator and open source.
- Formal description and simulator of pellets.
Study the formal description and language of the decomposition and combination of different functional cores, and build a 10-core integrated chip simulator based on the above description, which can accurately simulate at least 20 core behaviors such as computing, storage, IO, communication, and active silicon Interposer, and support the performance evaluation of more than 10 end/edge/cloud application scenarios. Realize formal description language simulator and open source.
- Access mechanism supporting cache consistency between cores.
The cache consistency mechanism of homogeneous/heterogeneous multi-core system is studied, and the multi-level cache architecture of integrated chip, extensible storage management mechanism and memory access optimization strategy based on network on chip are explored. The behavior model of cache consistency access between cores is constructed, which supports CC-NUMA architecture with a scale of more than 256 cores, with a typical delay of less than 100ns, and an open source functional verification simulator is provided.
- Power supply architecture and circuit for 10,000-watt integrated chips.
Study the high power density integrated power supply architecture and circuit, and explore the multi-level and low-loss power supply architecture for 10,000-watt integrated chips. Based on advanced packaging technology, a high-efficiency and high-power power supply circuit with the overall peak efficiency greater than 85% and the current density of the final DC-DC chip greater than 1.5A/mm2 is realized.
- Silicon-based optical interconnection interface circuit.
Study the silicon-based optical interconnection interface, explore high-bandwidth silicon optical devices, transceiver circuits compatible with CMOS technology, and heterogeneous integrated packaging technology, and realize a single-channel optical interconnection interface chip with a speed of more than 100Gbps, a bandwidth density of not less than 100Gbps/mm2, and an energy efficiency better than 4pJ/bit.
- Energy-efficient parallel interface circuit for core-particle interconnection.
The interface circuit of parallel interconnection with high energy efficiency and high density for 2.5D integrated inter-core interconnection is studied. Explore the multi-rate and multi-protocol compatible transceiver circuit architecture; Clock generation and recovery circuit with wide tuning range; Low power consumption equalization technology; Interconnection interface compatible with NRZ/PAM modulation mode. Realize the interconnection parallel interface circuit with the highest single-wire speed > 32Gb/s, the best energy efficiency ≤0.7pJ/bit and the bit error rate ≤1E-12.
- Layout and routing algorithm for large-scale core-particle interconnection.
This paper studies the fast and automatic layout and routing algorithm of large-scale core-particle interconnection, explores the signal integrity analysis method based on machine learning, the core-particle layout and interconnection routing algorithm driven by signal integrity, and the single/multi-objective optimization layout and routing algorithm with constraints, and realizes the integration of chip layout and routing EDA tools that support the scale of 100-core/100,000 interconnection lines and meet the signal integrity requirements of single-line rate greater than 16Gbps, and is open source.
Efficient electromagnetic field calculation method for 8. 2.5D integrated interconnection lines.
This paper studies the efficient electromagnetic field modeling method of layered, high-density and wide-band interconnection lines of integrated chips, explores the fast calculation method of layered Green’s function based on numerical path transformation algorithm, and the automatic and accelerated calculation technology of mesh generation, so as to realize the fast electromagnetic field simulator with Sign-off accuracy for interconnection lines with more than five layers of metal interconnection lines, edge wiring density not less than 300 IO/mm and frequency range covering 0-16GHz and open source.
- Basic theory of ultra-high density bonding and cross-scale mechanical model of interface.
The basic theory of ultra-high density direct bonding of stacking interface is studied, the stress-strain constitutive relation of interface under multi-field coupling is explored, and the cross-scale mechanical model of core-wafer bonding interface is established. The aligned connection of conductive interface arrays is more than or equal to 4× 104 pieces /mm2, and the high-reliability bonding with mechanical strength greater than 1.5 J/m2 is realized under the low-temperature annealing process at 180℃. Realize the high-density bond force simulation tool and open source.
- Warp model and stress optimization of large-size silicon substrate (Interposer) process.
Study the manufacturing technology of large-size silicon substrate, build wafer-level warping model and stress optimization method, explore the stress effect mechanism of manufacturing processes such as high aspect ratio TSV and high density deep trench capacitor, realize large-size silicon substrate ≥2400 mm2, and demonstrate that the warping value of 12-inch wafer after deep trench and silicon via processes is less than 200 μ m.. Realize the warping model simulation tool and open source.
4. Basic principles of project selection
(1) closely around the core scientific issues, pay attention to demand and application background constraints, and encourage original, basic and cross-cutting frontier exploration.
(2) give priority to funding research projects that can solve key technical problems in the field of integrated chips and have application prospects, and require the project results to be open source within the framework of this major research plan.
(3) key support projects should have a good research foundation and early accumulation, and have a direct contribution and support to the overall scientific objectives.
5. Funding Plan for 2023
It is planned to fund 10-20 cultivation projects, with an average funding intensity of about 800,000 yuan/project and a funding period of 3 years. The research period in the application for cultivation projects should be “January 1, 2024-December 31, 2026”; 7-10 key support projects are to be funded, with an average funding intensity of about 3 million yuan/project and a funding period of 4 years. The research period in the application for key support projects should be “January 1, 2024-December 31, 2027”.
6. Application Requirements and Precautions
(1) Application conditions.
The applicant for this major research project shall meet the following conditions:
1. Have the experience of undertaking basic research projects;
2 with senior professional and technical positions (titles).
Postdoctoral researchers in the station, those who are studying for graduate degrees, and those who have no work unit or whose unit is not a supporting unit may not apply as applicants.
(2) Provisions on application for restricted items.
Implement the relevant requirements specified in the “Application Provisions” of the 2023 National Natural Science Foundation Project Guide.
(3) Matters needing attention in application.
The applicant and the supporting unit shall carefully read and implement the relevant requirements in the project guide, the 2023 National Natural Science Foundation Project Guide and the Notice on the Application and Closing of the 2023 National Natural Science Foundation Project.
- This major research project is paperless. The application is submitted from September 1, 2023 to 16: 00 on September 7, 2023.
(1) The applicant shall fill in and submit the electronic application form and attachment materials online in accordance with the instructions for reporting and outline writing of major research projects in the network information system of NSFC.
(2) This major research plan aims to closely focus on the core scientific issues, conduct strategic direction guidance and advantage integration for multi-disciplinary related research, and become a project cluster. The applicant shall draw up the project name, scientific objectives, research contents, technical route and corresponding research funds by himself according to the specific scientific problem to be solved in this major research plan and the research direction to be funded by the project guide.
(3) In the application, the major research plan is selected as the funding category, the cultivation project or the key support project is selected as the subcategory description, and the scientific basis of integrated chip cutting-edge technology is selected as the note description. The acceptance code is T02, and no more than five application codes are selected according to the specific research content of the application project.
There shall be no more than 2 cooperative research units for cultivation projects and key support projects.
(4) In the “Project Basis and Research Content” part of the application, the applicant shall first state that the application conforms to the specific research direction in this project guide (indicating the research direction serial number and corresponding content in the guide) and its contribution to solving the core scientific problems of this major research plan and realizing the scientific objectives of this major research plan.
If the applicant has undertaken other scientific and technological projects related to this major research plan, it should discuss the differences and connections between the applied project and other related projects in the “research basis and working conditions” part of the main body of the application.
- The supporting unit shall, in accordance with the requirements, complete the commitment of the supporting unit, organize the application and review the application materials. Before 16: 00 on September 7, 2023, the electronic application form and attachment materials of the unit will be confirmed one by one through the information system, and the project application list of the unit will be submitted online before 16: 00 on September 8.
- Other precautions.
(1) In order to achieve the overall scientific objectives and multidisciplinary integration of major research programs, the project leaders who have received funding should promise to abide by the regulations on the management and sharing of relevant data and materials, and pay attention to the mutual support relationship with other projects in this major research program during the project implementation.
(2) In order to strengthen the academic exchange of the project and promote the formation of the project group and interdisciplinary integration, this major research plan will hold an annual academic exchange meeting of funded projects once a year, and will organize academic seminars in related fields from time to time. The person in charge of the funded project has the obligation to participate in the above-mentioned academic exchange activities organized by the guiding expert group and management working group of this major research plan.
(4) Consultation methods.
Division 2, Department of Interdisciplinary Science, National Natural Science Foundation of China
Tel: 010-62329489