Announcement on the Release of the 2024 Project Guidelines for the Major Research Plan on Scientific Basics of Frontier Technology of Integrated Chips
- Scientific objectives
This major research plan is oriented to the cutting-edge technology of integrated chips and focuses on the new issues brought about by the substantial increase in the integration level (number and type) of chip chips. It is planned to be conducted through the depth of disciplines such as integrated circuit science and engineering, computer science, mathematics, physics, chemistry and materials. Crossover and integration, explore new principles of integrated chip decomposition, combination and integration, and develop a new technological path based on independent integrated circuit technology to improve chip performance by 1-2 orders of magnitude, and cultivate a research team with international influence. Improve my country’s independent innovation capabilities in the chip field.
2. Core scientific issues
This major research plan focuses on the problems of decomposition, combination and integration of integrated chips after the number and types of core particles have been greatly increased, and focuses on the following three core scientific issues:
(1) Mathematical description and combinatorial optimization theory of core particles.
Explore the abstract mathematical description method of integrated chips and core particles, and construct the mapping, simulation and optimization theory of complex functions from integrated chips to core particles.
(2) Large-scale chip parallel architecture and design automation.
Explore the integrated chip design methodology after the chip integration level has been greatly improved, study multi-core interconnection architecture and circuits, layout and routing methods, etc., to support the design of hundred-core/ten thousand-core scale integrated chips.
(3) Multi-physics coupling mechanism and interface theory at the core particle scale.
Clarify the mutual coupling mechanism of electric-thermal-force multi-physics in integrated chips under the three-dimensional structure, build a fast and accurate simulation calculation method for multi-physics and multi-interface coupling at the core particle scale, and support the design and manufacturing of 3D integrated chips.
3. Research directions funded in 2024
(1) Cultivation projects.
Based on the above scientific issues and driven by the overall scientific goals, in 2024, it is planned to give priority to funding application projects that are exploratory, have original ideas, and propose new technological paths around the following research directions:
1. Core particle decomposition and reusable design method.
Research the formal description of integrated chips and core particles, decomposition-combination theory and modeling methods, and study reusable design methods of core particles such as computing/storage/interconnection/power/sensing/radio frequency.
2. Multi-core parallel processing and interconnection architecture.
Research on high computing power and scalable architecture for 2.5D/3D integration, interconnection networks and fault-tolerance mechanisms between cores such as computing/storage/communication, multi-core heterogeneous compilation tool chains, etc.
3. Integrated chip multi-field simulation and EDA.
Research on electro-thermal-mechanical coupling multi-physics calculation methods and rapid simulation tools for the core particle scale, integrated/layout/wiring automated design tools for integrated chips, testability design of integrated chips, etc.
4. Integrated chip circuit design technology.
Research on high-speed, energy-efficient serial/parallel, radio frequency/wireless, silicon optical interface circuits for 2.5D/3D integration, power management circuits and systems for high-power integrated chips, etc.
5. Integrated chip 2.5D/3D process technology.
Research the manufacturing technology of large-size silicon substrates (Interposer), high-density and high-reliability 2.5D/3D integration processes and materials, heat dissipation methods of 10,000-watt chips, optoelectronic integrated packaging processes, etc.
(2) Key support projects.
Based on the core scientific issues of this major research plan and driven by the overall scientific goal, in 2024, it is planned to give priority to funding application projects with good accumulation of early research results, strong cross-cutting, and greater contributions to the overall scientific goal:
1. Cache coherence and storage systems.
Study the cache coherence mechanism of heterogeneous multi-core systems, explore the multi-level cache architecture of integrated chips, scalable storage management mechanisms, and on-chip network-based memory access optimization strategies and quality of service (QoS) optimization mechanisms. Construct a behavior-level model of cache consistency between cores, supporting cache consistency between ≥ 2 types of heterogeneous cores (CPU, GPU, etc.), the total number of CPU cores ≥ 256, and the stable state of ≥ 7 cache lines. Typical latency is <200 cycles, and an open source functional verification simulator is available.
2. Core particle decomposition and combination optimization method.
For computing scenarios such as end-edge-cloud, study core particle decomposition and combination optimization theory, explore the functional representation of core particles, establish mapping of complex applications to core particles, study the stability and robustness of mapping theory, and form a complete Core particle library construction method. Compared with customized design, the performance loss is less than 20%, and the functional redundancy between core particles does not exceed 20%, forming a decomposition and combination tool and open source.
3. Layout and wiring method of multi-mask integrated chip.
With the goal of minimizing the number of mask layers and cross-mask interconnections in silicon substrate manufacturing, study the automated layout and wiring method of multi-mask integrated chips, and explore the TSV/interconnect line/deep trench capacitor process and design collaborative optimization method. Achieve an integrated chip layout and routing EDA tool that supports ≥4 times the mask area size and a total interconnection number of 100 cores ≥10 5 and open source.
4. Testability design method for integrated chips.
Research the integrated chip test bus architecture with high testability, plug-and-play and low overhead, break through the bottleneck caused by limited observable pins, explore hierarchical test scheduling and fault diagnosis technologies for integrated chips, and achieve testability Design EDA tools and open source them, with interconnection fault coverage ≥99% and test architecture hardware overhead ≤5%.
5. Energy-efficient chip-to-chip interconnect single-ended parallel interface circuit.
Research high-energy-efficiency, high-density 2.5D parallel interconnect interface circuit technology. Explore energy-efficient transceiver circuits and clock generation circuits with a wide tuning range; research reconfigurable technologies for signal encoding and equalization circuits for multiple interconnection standards and different channels; research anti-noise technology under extremely low transmit voltage swings. Achieving the highest single-line rate ≥32Gb/s, the best energy efficiency ≤0.5pJ/bit, compatible with NRZ/PAM interconnection parallel interface circuit, and open source simulation model.
6. Multi-field simulation algorithm and solver for core particle scale.
Research the electro-thermal-mechanical coupling model for the core particle integration process, explore the multi-physics simulation numerical method of the key structure, materials and interfaces of the integrated chip, realize automatic calculation grid division, develop a cross-scale multi-field simulation solver and Open source, the error range of calculation accuracy and experimental results is less than 10%.
7. Large-size silicon substrate manufacturing technology and warpage model and stress optimization.
Research large-size silicon substrate (Interposer) manufacturing technology, build wafer-level warpage models and stress optimization methods, and explore the stress of high-density, high-aspect-ratio through-silicon vias (TSV), deep trench capacitors (DTC) and other manufacturing processes The effect mechanism enables the preparation of silicon substrates with a size of ≥4 times the mask area, and realizes that the warpage value of the 12-inch wafer does not exceed 200 μm after processes such as deep trench capacitors and through-silicon vias. Establish wafer-level warpage analysis and prediction models, develop stress optimization simulation tools and open source them.
8. Three-dimensional integration of efficient heat dissipation materials and structures.
Explore the heat distribution characteristics and efficient heat transport mechanism under strong coupling of multiple hot spots, the integration of new heterogeneous heat dissipation materials and interface heat transport control methods, the structural design of micro-channel radiators and enhanced heat transfer methods. For 10,000-watt-level 3D integrated chip systems, the power of a single module in a 3D stack of cores is ≥2000W, the number of layers is ≥3, and the maximum heat flow density is ≥1000W/cm 2 . Complete multi-scale hotspot prediction and heat distribution simulation tools and efficient thermal management design tools and open source them.
(3) Integration projects.
This year, it is planned to select research directions with significant application value and good research foundation for integrated funding. The specific research directions are as follows:
1. Heterogeneous computing three-dimensional integrated chip.
Research cross-level collaborative design methods for three-dimensional integrated chips, explore modular combination and optimization methods of heterogeneous cores, and verify key technologies such as vertical power supply architecture and circuits, automated silicon substrate layout and wiring, and high-density core-wafer bonding. Develop a reusable active silicon substrate (Active Interposer) with a peak communication bandwidth of ≥1Tbps at the three-dimensional stacking interface. Realize heterogeneous computing three-dimensional integrated chip prototype, including at least 4 or more types of cores such as CPU, storage, and computing. The total number of heterogeneous cores is ≥16, the total storage is ≥512Mb, and the total computing power is ≥100TOPS. Realize heterogeneous computing on independent processes. The energy efficiency is higher than the level of GPU/NPU chips with the same computing power below 10nm. Complete the application verification of integrated chips in scenarios such as intelligent robots and edge computing.
4. Basic principles for project selection
(1) Closely focus on core scientific issues, pay attention to requirements and application background constraints, and encourage original, basic and cross-cutting frontier exploration.
(2) Prioritize funding for research projects that can solve key technical problems in the field of integrated chips and have application prospects, and require the project results to be open source within the framework of this major research plan.
(3) Key support projects should have a good research foundation and early accumulation, and have direct contribution and support to the overall scientific goals. Research institutions and enterprises are encouraged to apply jointly.
5. Funding plan for 2024
There are about 15 cultivation projects planned to be funded. The average funding intensity of direct costs is about 800,000 yuan per project. The funding period is 3 years. The research period in the cultivation project application form should be filled in “January 1, 2025 – December 31, 2027.” “”; it is planned to fund about 8 key support projects, the average funding intensity of direct costs is about 3 million yuan per project, and the funding period is 4 years. The research period in the application form for key support projects should be filled in “January 1, 2025 – December 31, 2028”; it is planned to fund 1 integrated project, the average funding intensity of direct costs is about 15 million yuan, and the funding period is 4 years. The research period in the integrated project application should be filled in “January 1, 2025 – December 31, 2028”.
6. Application requirements and precautions
(1) Application conditions.
Applicants for this major research plan project should meet the following conditions:
1. Have experience in undertaking basic research projects;
2. Have senior professional and technical positions (professional titles).
Postdoctoral researchers at the station, those who are pursuing a graduate degree, and those who do not have an employer or whose unit is not a supporting unit are not allowed to apply as applicants.
(2) Regulations on limited applications.
Implement the relevant requirements of the limited application provisions in the “Application Regulations” of the “2024 National Natural Science Foundation of China Project Guide”.
(3) Things to note when applying.
Applicants and supporting institutions should carefully read and implement the relevant requirements in this project guide, the “2024 National Natural Science Foundation of China Project Guide” and the “Notice on 2024 National Natural Science Foundation of China Project Application and Finalization and Other Related Matters”.
1. This major research plan project implements paperless application. The application submission date is from May 30, 2024 to 16:00 on June 5, 2024.
(1) Applicants should fill in and submit the electronic application form and attached materials online in accordance with the instructions and writing outline requirements for major research plan projects in the Science Fund Network Information System.
(2) This major research plan aims to closely focus on core scientific issues, strategically guide and integrate the advantages of multi-disciplinary related research, and form a project cluster. Applicants should formulate their own project name, scientific objectives, research content, technical routes and corresponding research funds based on the specific scientific problems to be solved by this major research plan and the research direction to be funded announced in the project guide.
(3) Select “Major Research Plan” for the funding category in the application, select “Cultivation Projects”, “Key Support Projects” or “Integrated Projects” for the subcategory description, select “Scientific Foundation of Integrated Chip Frontier Technology” for the annotation description, and select the acceptance code T02, and select no more than 5 application codes based on the specific research content of the application project.
The number of cooperative research units for cultivation projects and key support projects shall not exceed 2, and the number of cooperative research units for integrated projects shall not exceed 4 .
(4) The applicant should clearly state at the beginning of the application that the application is in line with the funded research direction in this project guide (state the research direction serial number and corresponding content in the guide), as well as its contribution to solving the core scientific problems and realizing the core scientific issues of this major research plan. Contribution to the scientific objectives of this major research program.
If the applicant has already undertaken other science and technology projects related to this major research plan, the differences and connections between the applied project and other related projects should be discussed in the “Research Basis and Working Conditions” section of the main body of the application.
- Submit the unit’s electronic application and attachment materials through the information system item by item before 16:00 on June 5, 2024, and submit the unit’s project application list online before 16:00 on June 6.
3. Other precautions.
(1) In order to achieve the overall scientific goals and multidisciplinary integration of major research plans, the project leader who receives funding should promise to abide by relevant data and information management and sharing regulations. During the project implementation process, attention should be paid to the relationship with other projects of this major research plan. mutually supportive relationship.
(2) In order to strengthen the academic exchanges of the project, promote the formation of project groups and multi-disciplinary intersection and integration, this major research plan will hold an annual academic exchange meeting for funded projects every year, and will organize academic seminars in related fields from time to time. meeting. The person in charge of the funded project is obliged to participate in the above-mentioned academic exchange activities organized by the guidance expert group and management working group of this major research plan.
(4) Consultation method.
Division 2, Interdisciplinary Science Department, National Natural Science Foundation of China
Contact number: 010-62327780